Our company has developed a series of IP Cores for video and image processing in FPGA devices:

	JPEG CoDec – we have developed a complete JPEG and Motion-JPEG compression and decompression IP core capable of 1080p at 60 frames per second. Our codec is fully compliant with the AXI4 interface specification and has been fully validated in Xilinx Zynq FPGA hardware.
	Non-uniformity and Defective Pixel Correction – we provide an IP solution for two-point linear video non-uniformity correction and defective pixel correction, often required in IR applications. The IP core is compact, AXI-Stream compliant, and fully programmable either through software or user logic in FPGA. The core has been validated on Zynq FPGA hardware, with the Sofradir LEO infrared detector.
	CameraLink and LVDS SerDes – serialized transmission of video is common accross a wide range of protocols. We provide a general-purpose, configurable serialization and deserialization solution for LVDS, with full CameraLink compliance. The IP core utilizes Xilinx SERDES and calibration resources and has been fully tested in Zynq FPGA hardware with several CameraLink and LVDS cameras.
	Contrast Enhancement and Dynamic Range Compression – synthetic color applications such as infrared imagery often require contrast enhancement to extract the detail present in the captured image. This is especially important in wide-range 14 bit actively cooled IR detectors such as the Sofradir LEO. Our AXI-Stream compliant IP core performs contrast limited adaptive histogram equalization (CLAHE) on monochrome images to reduce the dynamic range to industry-standard 8-bit while enhancing details in the image.